module hsia (
//------------------------------------
	clk,
	reset,
//------------------------------------
	pos_edge,
	neg_edge,
//------------------------------------
	clk_out
);

//-----------------------------------------------------------------------------
//	Parameter Declarations
//-----------------------------------------------------------------------------
parameter	CNT_NUM = 32'd5;

//-----------------------------------------------------------------------------
//	Port Declarations
//-----------------------------------------------------------------------------
input		clk;
input		reset;
//------------------------------------
output	reg	pos_edge;
output	reg	neg_edge;
//------------------------------------
output	reg	clk_out;

//-----------------------------------------------------------------------------
//	clock tick counter
//-----------------------------------------------------------------------------
reg		[31:0] counter;
//------------------------------------
always @(posedge clk or negedge reset) begin
	if (reset == 1'b0) begin
		counter <= 32'd0;
	end
	else if (counter == (CNT_NUM - 1'b1)) begin
		counter <= 32'd0;
	end
	else begin
		counter <= counter + 1'b1;
	end
end

//-----------------------------------------------------------------------------
//	the generation of clock out
//-----------------------------------------------------------------------------
always @(posedge clk or negedge reset) begin
	if (reset == 1'b0) begin
		clk_out <= 1'b0;
	end
	else if (counter == (CNT_NUM - 1'b1)) begin
		clk_out <= 1'b0;
	end
	else if (counter == (CNT_NUM >> 1)) begin
		clk_out <= 1'b1;
	end
	else begin
		clk_out <= clk_out;
	end
end

//-----------------------------------------------------------------------------
//	the generation of baud clock rising edge 
//-----------------------------------------------------------------------------
always @(posedge clk or negedge reset) begin
	if (reset == 1'b0) begin
		pos_edge <= 1'b0;
	end
	else if (counter == (CNT_NUM >> 1)) begin
		pos_edge <= 1'b1;
	end
	else begin
		pos_edge <= 1'b0;
	end
end

//-----------------------------------------------------------------------------
//	the generation of baud clock falling edge 
//-----------------------------------------------------------------------------
always @(posedge clk or negedge reset) begin
	if (reset == 1'b0) begin
		neg_edge <= 1'b0;
	end
	else if (counter == (CNT_NUM - 1'b1)) begin
		neg_edge <= 1'b1;
	end
	else begin
		neg_edge <= 1'b0;
	end
end

endmodule
